WIT Press


Characterization Of Deep Level Traps In Semiconductor Structures Using Numerical Experiments

Price

Free (open access)

Paper DOI

10.2495/MC150231

Volume

90

Pages

9

Page Range

253 - 261

Published

2015

Size

587 kb

Author(s)

A. Koel, T. Rang, G. Rang

Abstract

Deep level traps in the forbidden bandgap of semiconductor can be either a desired effect or technological harm that should be avoided. Understanding the essence of specific deep traps, their influence on electrical optical and mechanical characteristics of devices and circuits makes it possible to drive the manufacturing processes to maximize the desired effect. Deep level transient spectroscopy (DLTS) is one of the traditional methods for finding the trap levels in the semiconductor possible energy level bands. Majority carrier trap levels, concentrations and even location in the structure can be extracted from DLTS measurements. Finding parameter values for minority carriers is more complicated and needs extra efforts, combining DLTS with other measurements. Although DLTS, and its more advanced flavors like Laplace DLTS, can be utilized to measure trap parameters in semiconductors with high sensitivity, they do not determine the essence of the trap. Numerical simulations can be used to verify the influence of defect parameters on characteristics that are measured during DLTS. The simulation results and the DLTS measurement results carried out at the Thomas Johann Seebeck Department of Electronics are compared and discussed.

Keywords

numerical simulation, deep level traps, GaAs PiN diode