Author(s)

I. Tsukrov, W. M. Grich & T. S. Gross

Abstract

We propose the finite element simulation technique to model the process of diffusional creep and stress relaxation that occurs in Cu-damascene interconnects of integrated circuit devices in the processing stage. On the length scale of the interconnect lines (microns), the stress-induced mass flow constitutes the major mechanism of inelastic deformation. The mass flow problem is coupled to the stress analysis through vacancy flux and equilibrium vacancy concentration, allowing independently for the concentration profile and evolution of the stresses and strains in an iterative process to be solved. We decompose the total displacement field into the elastic part and the inelastic mass flow contribution. Performing the stress analysis in the configuration with accumulated inelastic displacements, we ensure that the shape of the interconnect line is compatible with external geometrical constraints throughout the simulation. This approach has been implemented in the software package that seamlessly integrates the problem-oriented code with the commercially available finite element program MSC.Marc. We apply the technique to model the Coble creep phenomenon by introducing the nanoscale grain boundary region having the thickness of the order of several layers of atoms. As an illustration, the problem of stress relaxation in a single grain subjected to prescribed displacements and tractions is examined. Keywords: copper interconnects, diffusional creep, grain boundary, nanoscale deformation, finite elements.

Keywords

copper interconnects, diffusional creep, grain boundary, nanoscale deformation, finite elements.