Author(s)

M. Dalpasso & M. Favalli

Abstract

Since fault-free CMOS digital integrated circuits are characterized by very low values of quiescent power-supply current (IDDQ), and the most part of their faults provoke abnormally high values of such current, IDDQ testing is one of the most effective way of testing them. The classical test pattern generation at the logic level is not accurate enough for IDDQ testing, be- cause the values of actual faulty current must be estimated and compared with the accuracy of the current monitor to decide on the fault detection; on the other side, electrical-level approaches are not feasible for VLSI ICs. The test pattern generation for IDDQ testing can be effectively performed with a mixed-level approach, featuring boolean manipulation by means of BDDs at the logic level, and using look-up tables for electrical-level data

Keywords