WIT Press

A Real Time SAR Processor Implementation With FPGA


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Page Range

435 - 444




2,439 kb

Paper DOI



WIT Press


C. Lesnik, A. Kawalec & P. Serafin


Great numerical complexity is a characteristic of synthetic aperture radar (SAR) image synthesis algorithms that poses a particularly serious problem for realtime application. Advances in the operating speed and density of the field programmable gate arrays (FPGA) have allowed many high-end signal processing applications to be solved in commercially available hardware. A realtime SAR image processor was designed and implemented with the commercial off the shelf (COTS) hardware. The hardware was based on the Xilinx Virtex 5 FPGA devices. Under the assumption of squinted SAR geometry and range migration effect present the SAR image synthesis algorithm was developed and implemented. The results of the processor tests conducted with simulated and real raw SAR signals are presented in the paper. Keywords: SAR, radar, real-time processing, FPGA, COTS. 1 Introduction Airborne radar systems constitute the essential part of radio-electronic terrain imaging and recognition systems. Their primary advantage is the insensitivity to the time of the day or atmospheric conditions. However the images obtained by radar characterises much lower than in the photographic case resolution. In the radar imaging two resolutions can be distinguished: the range resolution called also the fast-time resolution and the azimuth or the slow-time resolution. If the task of achieving the high range resolution is relatively easy - it is realized by using sounding signals with internal frequency or phase modulation or manipulation, the high azimuth resolution is much harder to achieve. It


SAR, radar, real-time processing, FPGA, COTS