Author(s)

E.B. Nowacka, P. Dewilde & T. Smedes

Abstract

We describe a hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to compute circuit models for layout dependent capac- itances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). New in the method are the models for the interface between the regions where the BEM and the FEM are applied. We show fast convergence of the method and give 2D and 3D simulation results which confirm its validity. I Introduction Parasitic interconnect capacitances in integrated circuits have significant influence on cir- cuit performance. To verify correct behavior of IC's before costly fabrication, these ca- pacitances must be calcu

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