WIT Press


Boundary Element Methods For Capacitance And Substrate Resistance Calculations In A VLSI Layout Verification Package

Price

Free (open access)

Paper DOI

10.2495/EL930391

Volume

3

Pages

8

Published

1993

Size

752 kb

Author(s)

T. Smedes, N.P. van der Meijs & A.J. van Genderen

Abstract

Boundary element methods for capacitance and substrate resistance calculations in a VLSI layout verification package T. Smedes, N.P. van der Meijs, A.J. van Genderen Delft University of Technology, Faculty of Electrical Emgmeermg, f 0 Boz 50&?, ATI-ggOO &4 D#, The Netherlands ABSTRACT In this paper we describe the application of the Boundary Element Method to the layout verification of VLSI Designs. We describe the methods for the cal- culation of interconnection capacitances and substrate resistances with the use of problem specific Green's functions. Emphasis is on computational efficiency and practical accuracy. The methods are implemented in the layout extractor Space (van der Meijs [1 ]). INTRODUCTION Designers of modern VLSI circuits rely heavily on layout-to-circuit extractors, which translate a chip layout into an equivalent network suitable for electrical verification of their layouts. Because of the growing influence of parasitic ele- ments, such extractors

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