Author(s)

S.Y.R. Hui, K.K. Fung, M.Q. Zhang & C. Christopoulos

Abstract

Generalised variable-time-step TLM technique for electrical circuit analysis S.Y.R. Hui,' K.K. Fung,* M.Q. Zhang/ C. Christopoulos' o Department of Electrical Engineering, University of Sydney, NSW 2006, Australia & School of Electrical Engineering, University of Technology, .Sydney, f 0 Boa; J23, Broadway, MSiy 2007, ,4WWm * Department of Electrical & Electronic Engineering, University of Nottingham, University Park, Nottingham ABSTRACT This paper describes a generalised variable time step technique (VTS) for the Transmission-line Modelling (TLM) method. The method is applied to electrical circuit analysis with emphasis on circuits which have widely separately time constants. The generalised technique enables easy handling of both the transient and steady-state behaviour of electrical circuits and allows a substantial reduction in the simulation time. The generalised VTS TLM algorithm can be applied to all TLM stubs and forms the basis for future auto-timestepping TLM methods for c

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