WIT Press


Acceleration Of Simulation Time By Hierarchical Modelling

Price

Free (open access)

Paper DOI

10.2495/EL930111

Volume

3

Pages

8

Published

1993

Size

580 kb

Author(s)

A. Hunger & A. Papathanasiou

Abstract

Acceleration of simulation time by hierarchical modelling A. Hunger, A. Papathanasiou Department for Dataprocessing, Faculty of Electrical and Electronic Engineering, University of Duisburg, Bismarckstr. 81, D-4100 Duisburg, Germany ABSTRACT The use of hierarchical data structures during the run time of simulation results in excellent performance values regarding model size and loading time without any loss of accuracy of the results. This paper describes the algorithms and techniques exploited by a hierarchical simulator and gives benchmark examples with regard to memory size and loading time for circuits of different size. Although this technique has been developed for the simulation of digital circuits, it is applicable to a broader spectrum of problems of discret simulation. INTRODUCTION Conventional simulators flatten hierarchical designs in order to get one netlist of the entire circuit with one-to-one correspondance between all physical nodes and t

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